1. Field of the Invention
The present invention relates to converting digital television signals coded according to an MPEG standard into standardized analog video signals (PAL, SECAM or NTSC).
2. Discussion of the Related Art
Television signal sources are more and more frequently digital sources, be it cabled networks, satellite transmissions, video storage digital disks, etc. Such sources require a conversion device for adapting the digital signals to the standardized inputs of a television set which are provided to receive standardized analog signals.
The transmission of digital television signals generally uses data compression, on the transmit side, to limit the amount of data to be transmitted. The information is compressed according to a predetermined standard (MPEG), prior to transmission. This requires that the information be decompressed, on the receive side, by the interface device, prior to converting the digital data flow into an analog data flow.
FIG. 1 shows, in the form of a block diagram, an example of conventional circuit for receiving digital television signals and for converting these signals into analog video signals.
At its input, the circuit shown in FIG. 1 includes a tuner 1 for, in particular, selecting one channel among several channels which are transmitted, for example, by a cabled network (not shown). The digital television signals corresponding to the selected channel are sent to a so-called "acquisition" circuit 2 for, in particular, extracting from the digital data flow a clock frequency corresponding to the transmission rate. Circuit 2 issues the digital television signals to a decompression circuit 3 for decompressing the data coded according to an MPEG standard. Circuit 3 issues a digital flow of images I in their display order to a coding unit 4 for coding flow I according to a PAL, SECAM, or NTSC standard and read out all components of the video signal and, especially, the horizontal and vertical synchronization signals. Unit 4 generally is associated with digital-to-analog converters (not shown) which issue analog video signals, for example, chrominance and luminance signals or a composite video signal.
A problem which arises in such a conversion circuit is the regulation of the video data flow output by unit 4 with respect to the input data flow issued by the transmission channel, in order to enable correct restitution of the images, for example on a television set (not shown).
For this purpose, two phase-locked loop (PLL) clock generators 5 and 6 are generally used. A first generator 5 is meant for generating a clock signal H1 based on the data flow from the transmission channel. This generator 5 generates the clock signal of the system before decompression to recover the received data and control the decompression performed by circuit 3 at the reception rate.
A second generator 6 generates a clock signal H2 for the data after decompression. This clock signal H2 is both used by coding unit 4 and for extracting the data from decompression circuit 3 at the display rate.
Decompression circuit 3 generally includes a field memory 7 which contains half-television images. These images are loaded into the memory at the rate of clock H1, and then are modified by decompression algorithms, and are read at the rate of clock H2 to be transmitted in the form of a flow of images I to unit 4. Two memory areas are generally alternatively used for reading and writing, a first area being written into to store the decoded images while a second area is read from to send the images to unit 4. Memory 7 generally is associated with a so-called "buffer" memory 8 to regulate the data flow when the read and write flows from and into the areas of memory 7 are unbalanced. Memories 7 and 8 are associated with a controller 9, the function of which is to organize the read and write operations from and into the different memories 7 and 8.
Controller 9 monitors the filling rate of buffer memory 8 to control clock H2 for reading from memories 7 and, thus to control the time base (not shown) of unit 4 which generates the synchronization signals included in the video signals and which uses this same clock H2 as a time reference. The horizontal synchronization signals H and vertical synchronization signals V from circuit 4 also are sent to circuit 3 to regulate reading from memory areas 7.
A disadvantage of a conventional circuit, such as shown in FIG. 1, is the necessary use of two clock generation phase-locked loops, which increases the cost of the circuit.
Another disadvantage is that, when the signal of read clock H2 is modified by PLL 6 to regulate the flow, the chrominance subcarrier contained in the composite video signal issued by unit 4 also is modified, since it depends on clock H2 which it uses as a time reference.